Deep trenches, typically having a depth exceeding 1 micrometer, or 1 micron, in contrast to shallow trenches having a depth less than 1 micron, are employed in the semiconductor industry to provide a variety of useful devices including a deep trench capacitor. The deep trenches may be utilized in a stand-alone semiconductor circuit such as a dynamic random access memory (DRAM) circuit to provide deep trench capacitors, or may be utilized as an embedded circuit component of a semiconductor chip that also includes other semiconductor circuits such as a processor core or other logic circuits. Particularly, embedded capacitors employing a deep trench are employed to enable an embedded memory device, e.g., an embedded dynamic random access memory (eDRAM) cell, a passive component of a radio frequency (RF) circuit, and decoupling capacitors that provide a stable voltage supply in a semiconductor circuit.
Hybrid orientation technology (HOT) provides multiple crystallographic orientations on the same semiconductor substrate. Specifically, a semiconductor-on-insulator (SOI) substrate containing a handle substrate, a buried insulator layer, and a top semiconductor layer is employed to form a hybrid orientation substrate. The handle substrate has the first crystallographic orientation, and the top semiconductor layer has a second crystallographic orientation, which is different from the first crystallographic orientation. An area of the SOI substrate is patterned to form a trench by removing a stack of the top semiconductor layer and the buried insulator layer and exposing the underlying handle substrate. After formation of dielectric spacers on the side walls of the trench, an epitaxially regrown semiconductor portion having the first crystallographic orientation is formed on the exposed portions of the handle substrate. Thus, a hybrid orientation substrate comprises two types of single crystalline surfaces having different crystallographic orientations. Differences in the two types of single crystalline surfaces may be advantageously employed to provide enhanced performances in semiconductor devices. For example, p-type field effect transistors may be formed on one type of single crystalline surface, while n-type field effect transistors may be formed on the other type of single crystalline surface.
High performance logic chips are frequently manufactured on an SOI substrate to provide enhanced performance over devices having comparable dimensions and manufactured on a bulk substrate. However, incorporation of embedded capacitors into the SOI substrate requires not only formation of deep trenches in the SOI substrate but also formation of a buried plate beneath a buried insulator layer, while preventing diffusion of dopants into a top semiconductor layer above the buried insulator layer. This problem is not alleviated even on a hybrid orientation substrate. Particularly, it is necessary to prevent diffusion of dopants into the top semiconductor layer to form a compact eDRAM cell. A spacer can be formed on the trench sidewall of the top semiconductor layer to prevent diffusion of dopants (see U.S. Pat. No. 6,566,177 to Radens et al., for example), but the spacer is susceptible to erosion during deep trench etch and consequently the integrity of the spacer is compromised.
In view of the above, there exists a need for a compact embedded dynamic random access memory (eDRAM) structure employing a deep trench capacitor compatible with a hybrid orientation substrate, and methods of manufacturing the same.